发明名称 |
Method for the selective deposition of a conductive material in the fabrication of integrated circuits |
摘要 |
The conductive material (14, 32) is deposited selectively, in an electroless process, on a catalytic surface forming the substrate. If the substrate is not catalytic, an activation step, for example by etching, is employed. In the process of electroless deposition to fill a through-hole to a substrate (10), there are deposited, after the formation of the hole in a dielectric layer (11) and exposure of the substrate, firstly a contact metal layer (15), followed by deposition thereon of a metallic barrier layer (16). The barrier layer metal is reacted with the substrate, with the formation of silicide. Then the contact filling material (14) is deposited in the hole selectively, in an electroless process, up to the desired level. <IMAGE>
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申请公布号 |
DE3815569(A1) |
申请公布日期 |
1988.12.29 |
申请号 |
DE19883815569 |
申请日期 |
1988.05.06 |
申请人 |
INTEL CORP., SANTA CLARA, CALIF., US |
发明人 |
TING, CHIU H., SARATOGA, CALIF., US;PAUNOVIC, MILAN, LONG ISLAND, N.Y., US |
分类号 |
H01L21/3205;H01L21/288;H01L21/768;H01L23/522;(IPC1-7):H01L21/88;C23C18/32;C23C18/38;C23C18/42;H01L21/90 |
主分类号 |
H01L21/3205 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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