| 摘要 |
A decoder circuit for a static random access memory cell and which may be integrated in monolithic form using gallium arsenide field effect transistors. The circuit comprises a first logic NOR-gate P1 having (n+1) inputs on which the n coded memory address signals or their complements are received, and also the chip-enable selection signal SB. The gate P1 is connected by a load resistor R to a supply voltage VDD1. A second NOR-gate P2 receives the same inputs as the gate P1 and has as its load a transistor T0 the gate electrode of which receives the output of the gate P1 and the drain of which is connected to a power supply voltage VDD2 which is less than VDD1. The voltage VDD2 is also the supply voltage for the memory cell, and is set at the clipping value of the gate junctions of the constituent transistors of that cell. The output VS of the decoder is produced at the drains of the transistors forming the second NOR-gate P2 which are connected to the source electrode of the load transistor T0. The inputs of the NOR-gates receive a chip-enable selection signal SB after application of the n coded memory address signals, thereby achieving reduced access time for the memory cell. |
