| 摘要 |
A 3-input Exclusive-OR gate circuit includes first, second and third inverters (M1, M2; M3, M4; M5, M6) having inputs adapted to receive first, second and third input signals, with the first and third inverters (M1, M2; M5, M6) having outputs coupled to first and second pairs of MOS gates (M11, M12; M7, M8) and the second inverter having an output coupled to an inverting means (M9, M10) which controls a pair of transmission gates (M14, M15; M16, M17) arranged to be alternatively operable. The current paths of the transmission gates (M14, M15; M16, M17) are coupled to outputs of the pairs of MOS gates (M11, M12; M7, M8) and have a common node (NB) which is coupled to a fourth inverter (M19, M20) which provides the circuit output. |
