Integrated processing unit, particularly for connected speech recognition systems.

摘要

In a two-level hierarchical system for connected speech recognition, wherein the lower level consists of one or more processing units, the circuit (RIPAC) according to the present invention constitutes one of the aforementioned units, which also provides for performing an additional internal test function. The structure features two internal data buses (BUSIN, BUSOUT) and internal memories for more commonly used data and addresses, for enabling high-speed microinstruction performance and external memory access. The external memory is divided into tables differing structurally but such as to be accessed in uniform manner by the internal addressing unit (ADB).