Integrated circuit with tub tie.

摘要

When making CMOS logic circuits, for example an inverter, it is frequently necessary to connect the sources of the p and n channel transistors to their respective tubs (n and p, respectively). The prior art required either a large contact window covering both source and tub regions, or else two standard size contact windows. The present technique forms the tub tie connection by the use of the same silicide layer (106,107,112,116) that is formed on the source/drain regions, which typically also forms a gate silicide (108,117) in the self-aligned silicide (i.e. "salicide") process. A conventional window may then be used to connect the silicide tub tie (and hence the source/tub regions) to a power supply conductor (114, 128). A space saving is obtained, and increased freedom for placing the power supply contact window is obtained.