发明名称 Semiconductor memory having a barrier transistor between a bit line and a sensing amplifier
摘要 In this invention, in a sensing circuit of a dynamic memory, barrier transistors are provided between the bit lines and the sensing amplifier. A circuit is provided that, on sensing and on data transfer, changes the gate potential of the barrier transistors so that during the sensing operation the barrier transistors are temporarily turned OFF, so that sensing can be carried out with high sensitivity, as the sensing system is not affected by the parasitic capacitance of the bit lines, while, on data transfer to the input/output lines, the gate potential of the barrier transistors is raised to a level greater than a value reached by adding the threshold value of the MOS transistors to the power source voltage, so that the conductance of the barrier transistors is increased, thereby speeding up the presensing of the input/output lines in the sensing circuit.
申请公布号 US4794569(A) 申请公布日期 1988.12.27
申请号 US19860863190 申请日期 1986.05.14
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 SAHARA, HIROSHI;TODA, HARUKI;OHSHIMA, SHIGEO
分类号 G11C11/409;G11C11/4094;G11C11/4096;(IPC1-7):G11C7/00 主分类号 G11C11/409
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