发明名称 ERROR VERIFYING SYSTEM
摘要 PURPOSE:To detect and recover a memory error is a main routine by generating an error in a memory in synchronism with a timer interruption, and providing an EGR instruction for returning in the main routine, and an EC instruction for verifying an error recovered state. CONSTITUTION:In the end of the interruption routine (subroutine), etc., of a timer, an EGR instruction is issued. It is decoded by an instruction decoding part 2, and when this is informed to an EGR instruction control circuit 3, error generating information is informed to a service processor SVP 5. The SVP 5 writes an error data and an error inspection bit in a memory, of an arbitrary part corresponding to this error generating information. Immediately thereafter, the processing is returned to a main routine and continued. Subsequently, when an EC instruction is issued in an error generation interruption routine, and information to an EC instruction control circuit 4 through the decoding part 2, error veryfying information is informed to the SVP 5, and whether a value which has been read out of the corresponding memory coincides with an expected value after an error has been recovered or not is verified.
申请公布号 JPS63318656(A) 申请公布日期 1988.12.27
申请号 JP19870155981 申请日期 1987.06.23
申请人 FUJITSU LTD 发明人 FUJIOKA SHUNTARO;IWATA KATSUYUKI
分类号 G06F12/16;G06F11/22 主分类号 G06F12/16
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