| 摘要 |
PURPOSE:To easily analyze a simulated result by incorporating a simulation model with an adding circuit storing output values in correspondence to both values when the output value of a front order part is not equal to an expected value. CONSTITUTION:When a simulation model prepared by a simulation model preparing part 1 includes a signal line 23 of an (n) bit constitution to connect blocks 21 and 22 and both, and the signal line 23 is selected by a signal line selecting part 2, an adding circuit incorporating part 3 is incorporated with an adding circuit 24 between blocks 21 and 22. For such a reason, a simulation part 4 simulates the logical action of the model to incorporate the circuit 24 in accordance with model to incorporate the circuit 24 in accordance with a verification pattern (c). At the time of the executing, the circuit 24 outputs the same value as the expected value to the block 22 regardless of the output value of the block 21, compares the output value and the expected value of the block 21 and stores both in correspondence when both are not coincident. Thus, even when an abnormality is present at the front step, a correct value is always added to the rear step, and the analysis of the result is facilitated.
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