| 摘要 |
PURPOSE:To surely and immediately detect the simultaneous processing and the cancelation of the simultaneous processing of (n) channels in (y) channels when they occur, by providing (n) counters which hold output levels by changing them when the number (y) of channels in one frame is counted and whose outputs are connected to an AND circuit. CONSTITUTION:A switching circuit 10 switches the counters (1-n) in order at every input of a processing detection signal outputted at the time of processing each CH, and the counters (1-n) cleared and start count operations vary and hold the output levels when the number (y) of the CHs in one frame is counted. The AND circuit 20 outputs a signal assuming that the simultaneous processing of (n) channels is detected while all of the counters (1-n) are operated. When an (n) CH simultaneous processing is performed during a time equivalent to one frame, the counter (n) is operated immediately, and since all of the (n) counters are operated, the (n) CH simultaneous processing is detected immediately, and also, when the (n) channel simultaneous processing is canceled, since at least one counter stops its operation, an (n) channel simultaneous processing cancel signal is detected surely and immediately.
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