| 摘要 |
PURPOSE:To prevent the occurrence of malfunction of the titled circuit even in the hit or abnormity of a synchronizing clock by allowing a counter circuit and a decoder to close the gate circuit thereby inhibiting the passing of a burst clock if an erroneous synchronizing signal is applied between synchronizing clocks. CONSTITUTION:The gate circuit 5 comprising an AND circuit is provided on the way of a line supplying a burst clock output of the gate circuit 4 to a serial/parallel conversion circuit 1. In the abnormity where a synchronizing clock signal is retarded by one clock, an output of a D FF6 subjected to one clock delay is overlapped partially with an output 255 of the decoder 3, an output of a D FF8 changes from '1' to '0' level, a '0' level signal is fed to the gate circuit 5 to inhibit the passing of the burst clock through the gate circuit. Moreover, the decoder output has a width of 2-clock or over because the input of the synchronizing clock is stopped to the counter 2 in case of the stop of the synchronizing clock, the transmission of the burst clock is stopped and the fetch of status information in the abnormity of synchronization is prevented.
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