| 摘要 |
PURPOSE:To cope with high-order input jitter by providing a data width extending circuit before a circuit which first processes input signal data with the timing clock signal extracted by a timing extracting circuit. CONSTITUTION:A circuit 11 which extends the width of input signal data is provided before circuits 9 and 10 which first process input signal data with the timing clock signal extracted by a timing extracting circuit 7. In flip flops 9 and 10, the processing is performed with a clock signal 8 extracted by the timing extracting circuit 7. Thus, the width of input data to flip flops 9 and 10 is extended by extraction in delay circuits 12 and 13 and phase margins of data and the clock of flip flops are improved to cope with a high-order jitter addition input signal. |
