发明名称 GALOIS FIELD ARITHMETIC UNIT
摘要 PURPOSE:To realize compatibility between high speed property and a small hardware quantity, by using a specific symbol on a result in which the output of a memory where a degree calculated result is stored is multiplied by a fixed coefficient. CONSTITUTION:The symbol in which an even-th bit from the low-order of a binary vector is 0 and an odd-th bit from the low-order is 1 is used as a multiplicand for the result in which a memory output where respective degree calculated result from oth-order to (t)th-order of an error position polinomial is stored is multiplied by the fixed coefficients from alpha<o> to alpha<t> respectively. In such a way, a bit component corresponding to the even square of (alpha) out of the outputs of fixed coefficient multiplier groups 1-8 goes to 0, and the exclusive OR of the multiplied result of only the fixed multiplier of odd square of (alpha) is taken, and it is possible to find a result X.sigma (X) that is the result obtained by substituting an error position in the polynomial where the error position polynomial is differentiated easily without performing specific calculation.
申请公布号 JPS63314919(A) 申请公布日期 1988.12.22
申请号 JP19870151861 申请日期 1987.06.18
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 MURAI KATSUMI;USUI MAKOTO
分类号 G06F11/10;H03M13/00 主分类号 G06F11/10
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