发明名称 Apparatus and method for accelerating floating point addition and subtraction operations by accelerating the effective substraction procedure.
摘要 <p>The arithmetic operations performed for floating point format numbers involve procedures having a multiplicity of major steps. The effective subtraction operation can be accelerated by using two methods of execution depending on whether the absolute value of the difference between the arguments of the exponents, ABS{DELTA(E)} is &lt;/=1 or &gt;1. The procedure for ABS{DELTA(E)}&lt;/=1 requires more major process steps than the situation where ABS{DELTA(E)}&gt;1. To accelerate only the procedure having more major process steps, the two least significant bits of both exponent arguments are examined and based on the examination, the lengthier procedure can be initiated in parallel with the process step determining the value of ABS{DELTA(E)}. When the lengthier procedure is determined to be inappropriate based on the determined value, the results of the lengthier process can be discarded. Otherwise, the lengthier process, already in progress, is continued.</p>
申请公布号 EP0296070(A2) 申请公布日期 1988.12.21
申请号 EP19880401538 申请日期 1988.06.20
申请人 DIGITAL EQUIPMENT CORPORATION 发明人 MAHESHWARI, VIJAY;SAMUDRALA, SRIDHAR;GAVRIELOV, NACHUM MOSHE
分类号 G06F7/485;G06F7/50 主分类号 G06F7/485
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