| 摘要 |
PURPOSE:To secure the connectivity of data by providing the titled circuit with a circuit for holding an access right until the completion of access to data with integer times the length of a data bus at the time of accessing one memory out of plural memories in plural CPUs and accessing the CPU and the memory by an output from the holding circuit. CONSTITUTION:The lowest-order bit signals LSB1, LSB2 of two CPU address buses and memory ready signals RDY1, RDY2 are inputted to a dual port memory arbitration circuit 12 and the circuit 12 is constituted of a memory access arbitration circuit 13 and a bus switching circuit 14. When a CPU access request signal MA1 and the signal LSB1 on one side are turned to 'L', its accessable signal SEL1 is turned to 'L' and connected to the memory, and even if the signal MA1 is turned to 'H', the signal SEL1 is held at 'L'. Even if the other CPU access request signal MA2 and the signal LSB2 are turned to 'L' under said state, an accessable signal SEL2 is kept at 'H', and even if the signals MA1, LSB1 are turned to 'L' and 'H' respectively, the signal SEL1 is held at 'L'. |
