| 摘要 |
PURPOSE:To efficiently execute memory access control by forming timing signals of address data and I/O data for a memory circuit in accordance with the memory access frequency of an I/O apparatus. CONSTITUTION:Input/output parts are sorted into an I/O part 2 for periodically accessing a memory 5 and an I/O part 3 for accessing the memory 5 like a burst. The I/O part 2 accepts a memory access request by hand-shaking with an address generating circuit 41 for generating an address to be accessed. The access control of the I/O part 3 is executed in each execution cycle of the memory circuit 5 and a memory address is generated from an address generating circuit 42.
|
