发明名称 DIGITAL SIGNAL PROCESSOR
摘要 PURPOSE:To facilitate a system control at the time of edition, etc., by setting a delayed amt. of data in an encoder and a decoder to be the multiple of integer of the length of a block blocked at the time of forming a transmission signal by the encoder. CONSTITUTION:Digital data DI supplied to a 1st input terminal 11 are coded for error correction by the encoder 13 and also blocked at every plural words to form a pseudo video signal VPO. The signal VPO is recorded to a VTR 20. A pseudo video signal VPI regenerated from the VTR 20 is supplied to the decoder 14 and decoded for error correction to be outputted as digital data DO. Now, the delayed amt. of the data in the encoder 13 and the decoder 14 is set up so as to set the sum of the delayed amt. of the same words being included in the data DI and the signal VPO and the delayed amt. of the same words being included in the signal VPI and data DO to be the multiple of integer of the block length blocked at the tie of recording. By this method, the system control at the time of edition, etc., can be facilitated.
申请公布号 JPS63313363(A) 申请公布日期 1988.12.21
申请号 JP19870148061 申请日期 1987.06.16
申请人 SONY CORP 发明人 TSUBAKI MASAMI
分类号 G11B20/12;G11B20/18 主分类号 G11B20/12
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