| 摘要 |
PURPOSE:To fetch only a correct data into a storage means at all times by fetching a read data into the storage means while the lock state of a phase locked loop (PLL) circuit is kept and not fetching the read data when the lock state is unlocked. CONSTITUTION:A revision inhibition means 63 is provided, which receives an input/output signal of a PLL circuit and inhibits an address revision of an address revision means in response to the output of an unlock detection means 22 detecting the unlocking of the PLL circuit. That is, the unlocking of the PLL circuit is detected and when the unlocking is detected, it is discriminated that the clock for data read is not normal to inhibit the address revision of the storage means storing the read data. Thus, only the normal data is fetched.
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