发明名称 SAMPLE-AND-HOLD CIRCUIT
摘要 PURPOSE:To reduce the settling time by selecting a value of a phase compensation capacitor in response to a hold capacitor so as to obtain an optimum transient response characteristic. CONSTITUTION:An input signal 6 is given to a noninverting input of an operational amplifier 1 and its output is given to a hold capacitor 4 and a buffer circuit 3 via a switch circuit 2 switched by a sample pulse 7 and the other terminal of the hold capacitor 6 is connected to ground and the output of the buffer circuit 3 is given to an inverting input of the operational amplifier 1 to constitute a feedback loop and the signal is fed back to an internal circuit of the operational amplifier 1 via the phase compensation capacitor 5. Through the constitution above, the switch 2 and the hold capacitor 4 form a low pass filter having a frequency characteristic different depending on the ON-resistance of the switch 2 and the value of the hold capacitor 4. Thus, in selecting the phase compensation capacitor 5 properly, the optimum transient response is obtained and the settling time is reduced.
申请公布号 JPS63311699(A) 申请公布日期 1988.12.20
申请号 JP19870147575 申请日期 1987.06.12
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 OKADA SHINJI;TAKIGUCHI MASAO
分类号 G11C27/02 主分类号 G11C27/02
代理机构 代理人
主权项
地址