| 摘要 |
PURPOSE:To prevent latch up by connecting a storage gate electrode to ground only for a prescribed period just after application of power supply so as to reduce power consumption thereby suppressing remarkably the rise in a base voltage just after the application of power voltage while keeping high circuit integration. CONSTITUTION:A period connecting a storage gate electrode 2 to ground is set by a waveform of a power-on reset signal V. Then the period is selected to a time or over when the power voltage VCC is made stable and a negative voltage V1 is supplied stably. Then the increase in the base voltage VBB after that is suppressed by the negative voltage V1 applied from a base voltage generating circuit similarly to a conventional circuit. Thus, just after the application of the power voltage VCC, the increase in the base voltage VBB is suppressed by the transfer of the electric charge into a capacitor C3 of the memory cell 1. Thus, even just after the application of the power voltage VCC, the remarkable increase in the base voltage VBB is suppressed to prevent generation of latch up. |
