发明名称 WRITE BUFFER CONTROL SYSTEM
摘要 PURPOSE:To ensure continuous memory writing actions at a high speed by storing data received from a device having a high processing speed in a write buffer in plural times and then transferring these data en bloc to a latch and also to a memory device via the latch and a bus. CONSTITUTION:A data processing part 2 stores successively the data to be written in a memory device 7 into a write buffer WB3 in plural times. When the last one of those divided data is stored in the WB3, all data stored in the WB3 are transferred en bloc to a WD4 to be held there and at the same time sent to a common data bus 6 via a buffer 5 to be written in the device 7. Thus the part 2 can carry out the next memory writing action from a cycle right after the last divided data is stored in the WB3. Then data can be written continuously in the device 7 at a high speed.
申请公布号 JPS63311453(A) 申请公布日期 1988.12.20
申请号 JP19870147277 申请日期 1987.06.12
申请人 FUJITSU LTD 发明人 TAKEI MASAYOSHI;MURATA TAKESHI;NODA TAKAHITO;KAMISAKA YUJI;ABO KENICHI;NONOMURA KAZUYASU;NISHIMACHI RIYOUICHI;SAKURAI YASUTOMO
分类号 G06F12/08 主分类号 G06F12/08
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