| 摘要 |
PURPOSE:To establish the synchronization for a frame reception time of a prescribed sequence number of times at all times by providing a means computing a reception clock and restoring the counter to the initial state after the count is finished when a bit error in a received synchronizing bit string is detected. CONSTITUTION:If a bit error takes place in a synchronizing bit string after the synchronization is established, a control circuit 9 outputs a control signal (k), and an adder 7 computes the bit number being the subtraction of the bit number from the head of the synchronizing bit string till the bit with a synchronizing fault detected therefrom from the sub of the bit number of the synchronizing bit string and the bit number of the data bit string. Moreover, an error bit counter 8 receives the control signal (k) to allow the adder 7 to start count- down. Then when a control signal (m) reaches a low level, a control circuit 9 outputs a control signal (i) to prevent the bit number of the predetermined synchronizing bit string to the synchronizing bit counter 2 to start the count. Thus, only the synchronizing bit string is compared with the normal bit string and the synchronization is established for a frame reception time of a prescribed sequence number of times. |
