| 摘要 |
PURPOSE:To contrive the improvement of the transfer speed by providing a bus switching means between a memory and a processing unit and coupling a bus via the bus switching means only when a processing unit accesses the memory or other processing unit so as to improve the utilizing rate of the bus. CONSTITUTION:The titled controller is provided with a memory 4 being a buffer at data transfer, plural processors 2-0, 2-1 sharing the memory 4, at least >=2 processing modules 1, 3 controlled by either the processor 2-0 or 2-1 respectively, and bus switching means 7-0, 7-1, 8-0, 8-1 using the processors 2-0, 2-1 and the processing modules 1, 3 corresponding to the processor as the processing unit between the processing unit and the memory. Then the communication between an LC 3 and a PU1 2-1 by a command is applied during the data transfer between the IFC 1 and BM 4 or the communication between the LC 3 and PU1 2-1 by a command is applied during the data transfer between the IFC 1 and BM 4. Thus, the interruption rate during data transfer is low and the effective utilization of the bus is attained.
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