| 摘要 |
PURPOSE:To simplify the multiplex interrupt processing by providing a flag commanding interrupt enable/inhibit state according to the priority depending on each cause to interrupt. CONSTITUTION:A CPU1 has a mask flag (I flag) 1a and connects to registers Ra-Rd corresponding to interrupt causes A-D and an enable register PR storing flags F3(a-d) commanding the interrupt enable/disable state according to the priority of each cause to interrupt. Moreover, the registers Ra-Rd have interrupt request flags F1(a-d) and interrupt enable flags F2(a-d). Outputs of AND gates Ga-Gd are given to the CPU1 as interrupt signals SI(a-d) when the level of an interrupt request flag F1, the interrupt enable flag F2 and the flag F3 is '1'. If the interrupt cause A having the highest priority is accepted by the CPU1, the content flag F3 of the register PR is saved and the other interrupt causes are not accepted, then '0000' is set to the register PR. |
