| 摘要 |
PURPOSE:To remarkably increase a processing speed by providing a priority bit detector, a parallel image data reducing circuit by a shift register masking circuit, and a word packing circuit. CONSTITUTION:When a mask pattern from a priority bit detector 3, an image data from a data latch 7, and a data which has shifted by bit the image data of the latch 7 from a shift register 9 are inputted, a masking circuit 5 refers to the mask pattern and allocates a picture element from the latch 7 and a picture element of the register 9, to a bit whose pattern is '1' and a bit whose pattern is '0', respectively, and thereafter, shifts 1 bit to an MSB side and outputs a processed data to the latch 7. By keeping pace with it, a shift register 4 shifts a mask pattern from the detector 3 by 1 bit to the MSB side, puts 1' into an LSB side and outputs a result to a pattern generator 2. The generator 2 takes OR of the original reduction bit instruction train and an input from the register 4, stores it as a new reduction bit instruction train and outputs it to the detector 3. When this processing is repeated and ended, its result is packed to word width. |
