| 摘要 |
<p>PURPOSE:To shorten synchronizing time without increasing so much a circuit scale even if the number of bits increases, by providing a first (m)-bit shift register, a second (m)-bit shift register, a comparing means and a counter. CONSTITUTION:A comparing means 18 compares a set fixed pattern outputted from the second (m)-bit shift register 20 and a data outputted from the first (m)-bit shift register 19. As a result, at the time of discrepancy, a data is shifted in a state that the set fixed pattern has been fixed, and at the time of coincidence, the set fixed pattern is brought to a circular shift by synchronizing with a shift of the data and compared. Subsequently, the number of times of coincidence is counted by a counter 21 and when it reaches a prescribed value, an output is sent out, thereafter, by a result of comparison of (n) bits, an error of the data is monitored. In such a way, even if the number of (m) bits increases, it is possible to cope therewith by increasing the number of bits of the registers 20, 19 and the comparing means 18 and the number of counting of the counter 21, and also, as for the time for taking a synchronization, since the set fixed pattern is brought to a circular shift, the synchronizing time can be shortened.</p> |
