发明名称 LOGIC CIRCUIT CHART RESTORING METHOD
摘要 PURPOSE:To facilitate the comparing collating of an original logic circuit chart and a restored logic circuit chart by obtaining a route whose logical gate number is a maximum as a main route and arranging the respective logical gates of the main route on one line along the flow of a signal. CONSTITUTION:By the connection information of a logical gate, the respective logical gate numbers of each route from an external unit terminal 1 to external terminals 2 and 9 are counted and the route whose logical gate number is a maximum is determined as a main route. Next, the respective logical gates 3, 4, 6 and 8 of the main route are arranged on one line along the flow of a signal. The respective logical gates of the rest besides the main route are successively added to the routes already arranged and arranged. Thus, the arrangement of the logical gate where the signal reverses is prevented and a restored logical circuit chart same as an original logical circuit is obtained. Accordingly, the comparing collating of the both is facilitated.
申请公布号 JPS63308674(A) 申请公布日期 1988.12.16
申请号 JP19870144253 申请日期 1987.06.10
申请人 FUJITSU LTD 发明人 OE RYOICHI
分类号 G01N21/88;G01N21/956;G06F17/50;H01L21/027;H01L21/30;H01L21/66 主分类号 G01N21/88
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