发明名称 INTERRUPTION PROCESSING CONTROL SYSTEM
摘要 PURPOSE:To execute a high speed host interruption processing by providing a holding means to combine a new program with the exceptional contents of a host CAT at the time of a guest interruption processing in a virtual computer to execute duplicate address transformation (DAT). CONSTITUTION:In a DAT where the actual address of a guest corresponds to the virtual address of a host, when the exception of a host DAT is detected during a guest interrupting processing, the state is immediately transitted to a host interruption by a state transition means 1. Then, a holding means 22 to combine the new program with the exceptional contents provided in a virtual computer is referred and the host interruption is executed by a processing means 3. Thus, the high speed host program interruption processing for the host DAT is executed without an emulation by a firmware.
申请公布号 JPS63308644(A) 申请公布日期 1988.12.16
申请号 JP19870144255 申请日期 1987.06.10
申请人 FUJITSU LTD 发明人 ASAKAWA GAKUO;INOUE AIICHIRO
分类号 G06F12/10;G06F9/46;G06F9/48 主分类号 G06F12/10
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