| 摘要 |
PURPOSE:To simultaneously transmit a former half part and a latter half part in serial plural data by the use of one memory, by forming an address signal as prescribed. CONSTITUTION:A DMA controller 54 consists of a counter 56 and a multiplexer circuit (MPX) 58. The counter 54 generates the counting signals 1c-9c of a prescribed bit number indicating accumulative counted value by counting a clock signal f1 and supplies them to the MPX 58. At the time of writing, the MPX 58 shifts the highest order digit bit to the lowest order bit in the counting signal, and at the same time, it gives the remaining bits in the counting signal to be respectively shifted to high order by one digit, to a line buffer 50 as an address signal. At the time of reading, the counting signal is given to the buffer 50 as an address signal as it is. Thus, a purpose can be attained.
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