| 摘要 |
PURPOSE:To optimize the relation of time between a start control signal and a write pulse by providing a timing generating circuit generating a write pulse satisfying a prescribed timing condition under a start control signal supplied externally. CONSTITUTION:A write enable signal, the inverse of WE is fed to a timing generating circuit TG in the same timing as the address signal and an input write data. A strobe signal is generated with a slight delay to chip select signal, the inverse of CS, the strobe signal is used as a trigger signal and a latch FF1 is set or reset selectively according to the signal, the inverse of WE. Moreover, the write pulse phiw is formed selectively while keeping a prescribed time with the signal, the inverse of CS according to the state of the latch FF1. The relation of time is optimized so that the memory cycle of the bipolar RAM is the highest. Thus, the timing condition with respect to the signal, the inverse of WE of the bipolar RAM is relaxed and the memory cycle is quickened.
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