| 摘要 |
PURPOSE:To improve the performance of a memory device by providing a flag memory circuit which can rewrite a flag bit in response to an are address of the memory part in the memory device having plural types of memory parts of different access speeds. CONSTITUTION:The address space of a memory 1 is divided into a high-speed access area and a low-speed access area and a flag bit is set at a flag memory circuit 5 in response to each access area. Then the flag bit of the circuit 5 provided in a memory control circuit 2 is read out by means of a higher level bit of the address stored in an address register 4 and then inputted to an access timing control circuit 6. The circuit 6 applies the timing control signals of different speeds to the memory 1 in response to the flag bit. The circuit 5 can set a flag bit in accordance with the dividing state of the address space and therefore can set optionally an address range. As a result, the performance of the device is improved.
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