| 摘要 |
The main circuit 2 of the adder circuit according to the subject of the invention does not consist of individual adder circuits, because the AND circuits which are used are driven at one input by a through line p, and only process the value 2. For processing the value 1, a dual full adder 6 is thus required, and for processing the value 5, a dual full adder 7 is also required. The main circuit 2 consists only of eight AND circuits 9 each with two inputs, and eight OR circuits 10 each with two inputs. If the intermediate result number is greater than the number 4, a partial sum with the value 5 is derived from this, and processed in the dual full adder 7. Circuit 4 is a one upwards shift circuit, which is combined with a straight-through circuit. <IMAGE>
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