| 摘要 |
<p>A pipeline memory structure having a plurality of randomly accessible memory units (128, 130) and a hierarchical arrangement of data input, data output and address memory interface registers. The data input and address registers are used to distribute data and address information to the memory units from a data input port (112) and an address port (116) of the processor of a computer, while the data output registers are used for collecting data information from the memory units and directing this data information to a data output port (114) of the processor. The data input, the data output and address registers each comprise a plurality of memory interface units (120, 124, 126) which are inter-connected together to form separate branched-tree structures having a plurality of levels.</p> |
