发明名称 FSK DEMODULATING CIRCUIT
摘要 PURPOSE:To reduce the quantity of hardware and to form an LCI chip by providing a control circuit which presets a complement of 2 to a criterion in a zero-cross interval measuring counter according to the detection of zero-cross points and starts measurement. CONSTITUTION:A complement of 2 to a threshold period from a memory 301 is preset in a counter 302 for each zero-cross point at the start of measurement, zero-cross intervals in one section are measured, and the threshold period is a criterion used when a binary signal is decided from the measured value of the counter. The measurement result is stored in a register 402 through a selector 401 and the contents of the register 402 are shifted to a low-order register at the same time. Then, an accumulation register is cleared and when the contents of shift registers 402-405 are circulated by one round through the selector 401, an adder sums up the outputs of the register 405 and accumulation register 407, so that the sum is stored after the contents of the registers 402-405 are shifted by one round. Consequently, the number of bits is small and the hardware quantity may be small.
申请公布号 JPS63308451(A) 申请公布日期 1988.12.15
申请号 JP19880124159 申请日期 1988.05.20
申请人 SEIKO EPSON CORP 发明人 TAKEDA KOJI;AKAHA MASAO;MUKOYAMA FUMIAKI;KUDO YASUHIKO
分类号 H04L27/156;H04L27/14 主分类号 H04L27/156
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