发明名称 HIGH FUNCTION Z BUFFER MEMORY
摘要 PURPOSE:To remarkably curtail the time required for generating an image, by providing a comparing and cumulating circuit on each memory unit, and also, providing an increment circuit for setting an initial value of a depth value and an increment. CONSTITUTION:To each of memory elements MEMi, a comparing and cumulating circuit (I=0-7) consisting of an arithmetic logical arithmetic unit ALUi, a cumulative adder ACCi and a gate Gi is added, and also an increment circuit 3 for setting an initial value of a depth value and increment is provided. The increment circuit 3 sets an initial value of a depth value and an increment of a horizontal line portion to be brought to picture drawing, and supplies them to a comparing and cumulating circuit of each system through a broadcasting bus 4. Each comparing and cumulating circuit executes a cumulative addition of the value, based on a data from the increment circuit 3, by a separate designation, and writes it in the memory element. In such a way, a series of processings such as read-out of a memory at the time of a hidden surface erasion processing, (z) comparision, conditional write and cumulative addition can be executed simultaneously as to an 8-picture element portion in the inside of the memory unit, and the time required for generating an image is remarkably reduced.
申请公布号 JPS63307591(A) 申请公布日期 1988.12.15
申请号 JP19870142181 申请日期 1987.06.09
申请人 AGENCY OF IND SCIENCE & TECHNOL 发明人 YOSHIDA TAKAYOSHI;OYA IKUO;WAUKE YASUSHI
分类号 G06T15/00;G06T15/40 主分类号 G06T15/00
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