Semiconductor memory device.

摘要

A semiconductor memory device includes a memory cell (MC) including: a volatile memory cell portion (1) with a flip-flop (Q1 SIMILAR Q4); and a non-volatile memory cell portion (2, 2A) provided for the volatile memory cell portion on a one-to-one basis and including a capacitor portion (FC) operatively connected to the volatile memory cell portion, a memory transistor (QM) operatively connected to the capacitor portion, and a recall transistor (QR) connected between the memory transistor and one of a pair of nodes (N1, N2) of the flip-flop and being turned ON in a recall operation. By constituting the capacitor portion so that it has a structure formed by a capacitor (Cf) and a tunnel capacitor (TC) used in a store operation connected in series and receives a difference voltage between voltages appearing at the pair of nodes, it is possible to reduce a space occupied by memory cells on a chip and to raise a degree of integration of the circuit.