发明名称 PACKAGE FOR PIN GRID ARRAY
摘要 <p>PURPOSE:To decrease the number of pins by making internal pin members, to which external leading-out pins are disposed in a coaxial manner through insulating members in themselves, longer than external pin members and conducting each pin member with a wiring layer formed to a substrate intermediate layer. CONSTITUTION:A printed substrate has a substrate upper layer 27, a substrate lower layer 30 and a substrate intermediate layer 29, which is arranged between the layer 27 and the layer 30 and to which a wiring layer 28 is shaped. A first pin member 31 in external leading-out pins takes a cylindrical shape, and an insulating member 34 consisting of a cylindrical heat-resistant insulating resin is press-fitted to the first pin member 31. A ring-shaped second pin member 32 is press-fitted to the insulating member 34, and the first pin member 31 and the second pin member 32 are disposed in a coaxial manner through the insulating member 34. The lengths or positions of the lower edges of the first pin member 31, the second pin member 32 and the insulating member 34 differ: the first pin member 31 is largest, and the second pin member 32 is shortest. Accordingly, the number of the pins in the substrate can be decreased.</p>
申请公布号 JPS63305542(A) 申请公布日期 1988.12.13
申请号 JP19870140769 申请日期 1987.06.06
申请人 NEC CORP 发明人 YAMASHITA TSUTOMU;ASHIHARA HIROTAKA
分类号 H01L23/50 主分类号 H01L23/50
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