| 摘要 |
PURPOSE:To obtain an output signal with higher accuracy than that of an output of a conventional phase comparator from the beginning by applying the phase comparison for plural signals in the lump in a digital PLL circuit. CONSTITUTION:A fixed frequency oscillator 1A operated at a frequency close to that of an input signal 100 is used and a delay circuit 1 is prepared, which consists of N-set of delay elements giving a delay of a predetermined time taufor each tap connected in cascade. The input signal 100 is inputted to the N-set of phase comparison elements of the phase comparator 2 and the phase comparison is applied in the predetermined sampling timing with the N-set of delayed fixed frequency signals. An encoder 3 converts the output of the phase comparator into leading position information of the retarded fixed frequency signal when the result of comparison is inverted and a selection circuit 4 selects a signal retarding the output of the fixed frequency oscillator in phase synchronization with the input signal. |
