发明名称 INTER-PROCESSOR COMMUNICATION SYSTEM
摘要 PURPOSE:To reduce overhead at the time of simultaneous transfer of the same message to plural processors by storing a message and the number of receiving processors at the tie of transmission, and at the time of reception, reading out the message and then updating a processor counter. CONSTITUTION:Communication buffers 410 are formed in a common memory 400 correspondingly to respective processors 200a-200c. At the time of transmission, a message and the number of receiving processors are recorded in the communication buffer 410 of a self processor, an interruption is simultaneously generated in plural processors and an instruction for informing processor numbers is executed. The receiving processor reads out a message from the communication buffer 410 of the transmitting processor, subtracts '1' from the number of processors stored in the buffer 410 and stores the processor No. of the self processor. Since the communication buffer 410 is formed in each processor, and at the time of communication to plural processors, a message is stored in the communication buffer of the self-processor, message storage overhead can be reduced.
申请公布号 JPS63305450(A) 申请公布日期 1988.12.13
申请号 JP19870141458 申请日期 1987.06.08
申请人 HITACHI LTD 发明人 KATADA HISASHI;TAKEDA KATSUMI
分类号 G06F15/16;G06F15/167;G06F15/177 主分类号 G06F15/16
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