发明名称 |
Digital phase-locked loop with random walk filter |
摘要 |
A digital phase-locked loop in which the lead or lag of the phase of the input is compared to the phase of the output of the loop and the occurrences of the advance or retardation are filtered in a random walk filter in order to phase control the output. According to the invention, the time trend of the advance or retardation is determined. If there is a significant run of either advance or retardation, the random walk filter is adjusted so as to more quickly provide correcting output.
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申请公布号 |
US4791386(A) |
申请公布日期 |
1988.12.13 |
申请号 |
US19870069121 |
申请日期 |
1987.07.02 |
申请人 |
SUMITOMO ELECTRIC INDUSTRIES, LTD. |
发明人 |
SHIGA, NOBUO |
分类号 |
H03L7/06;H03L7/089;H03L7/099;H03L7/107;(IPC1-7):H03L7/08 |
主分类号 |
H03L7/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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