| 摘要 |
PURPOSE:To improve data transfer capacity between an instruction processor and a storage device by transferring writing data following data reading through an address signal line during the transfer of preceding reading data through a data signal line. CONSTITUTION:Plural RAMs in the storage device are divided into plural groups 101-124 to reduce the load of drivers 11, 21, 31 for driving the RAMs and to shorten wiring. Since the drivers 11, 21, 31 are respectively provided with address registers 12, 23, 33 and data registers 14, 24, 34, the storage device 2 can be accessed through a pipe line. On the other hand, RAM access is controlled so as not to be waited because writing data are not transferred due to transfer collision between reading data and writing data. Consequently, the storage device can be accessed twice per machine cycle, so that data transfer capacity equivalent to the installation of an instruction buffer storage device and a data buffer storage device can be obtained.
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