| 摘要 |
PURPOSE:To speed up a computing time by preparing two outputs, one is an arithmetic output arithmetically computed by denying the existence of carry from the low-order side, and the other is an arithmetic output logically computed by accepting the existence of carry, for the high-order side, and selecting an appropriate one out of the two arithmetic outputs in accordance with the existence of the carry from the low- order side. CONSTITUTION:In parallel adders A1, A2, bits are divided into high-order bits and low-order bits, and their parallel operation is independently executed. Since the result of the operation of the high-order bit is varied in accordance with the existence of carry from the low-order bit side, the operation of the high-order bit is executed under a no-carry state, and when the arithmetic output is inputted to a logical circuit 16, an operation result corresponding to the existence of the carry is found out. On the other hand, the output of the logical circuit 16 or the arithmetic output of the high-order side is selected in accordance with the existence of carry at the time of determining the output of carry from the low-order side as the final arithmetic result of the high-order side. Consequently, the final arithmetic result is obtained at the time of transmitting 8 bits out of 16 bits of carry from the low-order side to the high-order side, and determining them, so that the computing time can be reduced into a half.
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