| 摘要 |
PURPOSE:To perform data transfer at high speed, by providing two mask registers which represent the effective bit position of a leading address and that of the final address. CONSTITUTION:The effective bit of transfer destination data at the forefront of continuous addresses shown at an address register (AR)5 is written on a memory 20 by a first mask register which holds effective bit information of the computed result of a computing element 3. Transfer in a word unit is performed in such a way that a flip-flop 16 is reset, and the output of the computing element 3 is written on the memory 20 assuming that all of the bits are effective. The effective bit of the final transfer destination data of the continuous addresses is written on the memory 20 by selecting a second mask register which holds the computed effective bit information of the computing element 3. In such a way, it is possible to perform the data transfer to the memory in a bit unit in the memory possible to be accessed only in the word unit.
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