| 摘要 |
PURPOSE:To prevent the increase of the number of lines of address input even if a memory capacity is increased by selecting a memory cell array according to a high-order address by using an address register and a plane decoder for the high-order address. CONSTITUTION:When 0 address is designated in a row address buffer 103 and a column address buffer 111, an input/output data control circuit 112 selects the high-order address register 101, and the high-order address through an I/O 1 and I/O 2 is stored in the register 101. Then, the corresponding memory cell arrays 105-108 are selected through the plane decoder 102, and the selected memory cell array is accessed through a row decoder 104, a column decoder 110. By this constitution, even if the memory capacity is increased by increasing the memory cell array, the number of lines of the input address can be suppressed not to increase, and without increasing the address output, outputted from a CPU, and besides, without any externally extended circuit, a RAM can be accessed without increasing the number of package pins.
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