发明名称 PARALLEL PROCESSOR
摘要 PURPOSE:To fetch a message in a receiving processor in sequence of arrival, by providing an main identifier which identifies a data group and a sub identifier which identifies data in a data identifier. CONSTITUTION:Processor elements (PE) 2-1-2-3 with the same constitution are connected with a data transfer path 1. The PE is provided with a memory 3, a message generating transmitter 6 which constitutes the message from a transmission destination PE under, data to be transmitted, and the identifier MK and the identifier SK alloted for them and sends them to the transfer path 1, and an associated memory 8 in which the transmission destination PE number in the message and a time message addressed to its own from the transfer path 1 is fetched via an input buffer 7. The message fetched in the associated memory 8 is processed by referring to the identifiers MK and SK of each message.
申请公布号 JPS63303460(A) 申请公布日期 1988.12.12
申请号 JP19880008315 申请日期 1988.01.20
申请人 HITACHI LTD 发明人 TANAKA TERUO;HAMANAKA NAOKI;OMODA KOICHIRO;NAKAKOSHI JUNJI;NAGASHIMA SHIGEO
分类号 G06F15/17;G06F15/173;G06F15/80;G06F17/16 主分类号 G06F15/17
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