发明名称 DIGITAL FREQUENCY TUNING CIRCUIT
摘要 PURPOSE:To improve the S/N as a frequency tuning circuit by providing a sample and hold circuit between an output side of a low pass filter in a phase locked loop and an input side of a voltage controlled oscillator so as to attenu ate the noise of a phase comparator. CONSTITUTION:An oscillation output of a voltage controlled oscillator 1 is frequency-divided by a designated prescribed count and given to a phase compa rator 3, where the frequency division frequency and a reference frequency fr are compared and the result is subject to Miller integration at a low pass filter 4 as an output 101 and inputted to a sample and hold circuit 5 as an output 102. The integration output 102 is sampled in the sample and hold circuit 5 synchronously with the reference frequency fr. Then the sampling value is held and given to the voltage controlled oscillator 1 as a steady-state control voltage signal 103. The oscillation frequency of the oscillator 1 is controlled by the voltage signal 103 to form a phase locked loop. The noise is eliminated from the sample and hold circuit 5 from the control voltage signal 103.
申请公布号 JPS63300617(A) 申请公布日期 1988.12.07
申请号 JP19870137234 申请日期 1987.05.29
申请人 NEC CORP 发明人 GOTO FUMIO;SATO HIDEKI
分类号 H03J7/18;H04B1/26 主分类号 H03J7/18
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