| 摘要 |
PURPOSE:To obtain a PLL frequency synthesizer obtaining a now noise characteristic by switching the gain of a loop filter in response to the order of frequency-division even when the ratio of an upper limit Nmax and a lower limit Nmin of the output frequency of a synthesizer is large. CONSTITUTION:In inputting 2 control signal selectively to control signal input terminals 15a-15d, an optional resistor in resistors 9a-9d is selected and connected in parallel with a resistor 5. In assuming a resistance between the active filter 3 and the resistor 5 as R'1, when the value R'1 is selected to suppress the change in the open loop gain due to the change in the frequency division order N to bring the open loop gain to be Gaf at all times, a low noise PLL frequency synthesizer output is obtained. The open loop gain Gaf is denoted by equation I, and switches 12a-12d are subject to switch control selectively by using an external control signal so as to satisfy equation II by the resistance R'1 with respect to the frequency division degree N. As a result, the open loop gain is always selected to be Gaf to extract a low noise output over a broad band. |
