| 摘要 |
PURPOSE:To receive data in parallel with arithmetic processing and to shorten a data transfer time by allowing the processing circuit in a 2nd processor to perform arithmetic processing by the use of the storage contents of remaining memories which are not receiving data from a 1st processor among plural memories. CONSTITUTION:The data transferred from the 1st processor U11 are switched in order and stored in the plural memories B in the 2nd processor U12. The processing circuit 14 provided in the 2nd processor U12, on the other hand, performs the arithmetic processing by using the storage contents of the remaining memories which are not receiving the data from the 1st processor U11 among the plural memories B. The data can be received in parallel with the arithmetic processing of the processing circuit 14 to shorten the time for the data transfer.
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