| 摘要 |
PURPOSE:To attain high speed decoding processing by providing a symbol memory, a reversible shift register, a selector and a FF, then simultaneously executing reception symbol and pathmetric operation. CONSTITUTION:A symbol memory 1 is subject to read control according to the path decision and a read reception symbol is fed to a shift register 2. The shift direction control is applied to the register 2 according to forward or backward path retrieval and a reception symbol being the output of a prescribed stage is fed to a selector 3. The selection control is applied to the selector 3 corresponding to the forward or backward path retrieval, the reception symbol being the output is stored in a FF 4 and fed to a pathmetric arithmetic section. Since high speed operation is attained for the register 2 and the selector 3 in comparison with the memory 1, the reception symbol read before and stored in the register 2 is outputted selectively and immediate operation is attained via the FF 4. Thus, the readout of recepetion symbol and the arithmetic operation of the pathmetric are executed in parallel, and the decoding processing is quickened.
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