发明名称 MASTER SLICE TYPE SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PURPOSE:To increase the degree of freedoms of a logic design by controlling a switch circuit inserted between a column selector, a sense amplifier of a memory circuit contained in a master slice type LSI and a light amplifier by a control circuit prepared in advance in the memory circuit. CONSTITUTION:When a seventh address 39 is 0 level, switch circuits 34, 36 are conductive and switches 35, 37 are interrupted. Accordingly, the data of a first memory cell array 2 selected by first-sixth address inputs 12-17 are applied to the input of a sense amplifier 18 at the time of reading. A signal applied to a data input terminal 30 is written in memory cells selected by the inputs 12-17 of the array 2 at the time or writing. Similarly, the memory cells selected by the inputs 12-17 of a memory cell array 4 are accessed from terminals 28, 31. When seventh address input 39 is '1', the switches 35, 37 become conductive, and the arrays 3, 5 can be respectively accessed from terminals 26, 30 and 28, 32.
申请公布号 JPS63300527(A) 申请公布日期 1988.12.07
申请号 JP19870136887 申请日期 1987.05.29
申请人 NEC CORP 发明人 MATSUURA HIDEKI
分类号 H01L27/118;G11C11/41;H01L21/82;H01L21/822;H01L21/8242;H01L27/02;H01L27/04;H01L27/10;H01L27/108 主分类号 H01L27/118
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