| 摘要 |
PURPOSE:To prevent an erroneous selective response signal from being returned at the time of high speed access by using a delay element to decrease the output pulse width of a D type FF in receiving a selection signal and to quicken the restoration of L to H in the delay element output. CONSTITUTION:The R output is at H when the D type FF 15 for selective response signal output is in a non-selection state and when the selection signal (a) goes to L, the Q output of D FF 14 goes also to L. The output of Q is given to a delay line 1, a signal (g) of L level retarded by a prescribed time is outputted from a tap and given to a reset terminal, the inverse of R of the FF 14. Thus, the level of the signal (e) changes from L to H and the signal (a) is converted into a signal with a short pulse width. The signal (h) goes again from L to H after the returning time of the selective response signal (f) the FF 15 latches the output signal (d). Thus, the signal (f) is returned to an access device via a tri-state gate element 3. When the H signal is returned from the access device, the R input of the FF 15 goes to H and the signal (f) goes to H.
|
